As application specific integrated circuit (ASIC) designs continue to advance in both performance and complexity, the designs become more susceptible to timing problems. In turn, more effort and time is spent on static timing analysis to understand the timing relationships of the various clocks generated within the designs. No simple mechanism exists in conventional static timing analysis tools to accurately define the clock relationships in the designs. Clock timing relationship analysis commonly becomes a manual process introducing inaccuracies and translation mistakes that result in timing errors in the design. The manual analysis problems are amplified further if predefined clocks are used in both pre-layout and post-layout analyses, where multiple clocks are defined through the process of consistent and accurate extraction of clock information from an estimated pre-layout standard delay format (SDF) file or a post-layout SDF file.
For complex ASIC designs, only experienced ASIC engineers can perform static timing analysis using the existing approaches. The ASIC engineers will prepare clock definitions and constraints (i.e., multi-cycle paths and false paths) for the static timing analysis. Even still, the timing results are easily affected by peculiarities of the tools. The wrong results will be generated if the tool does not understand the clock definitions correctly. Several tools are currently available that are used to perform static timing analysis on entire ASIC designs. Examples of conventional static timing analysis tools are TimeMill®, PrimeTime® and MOTIVE® (all registered trademarks of Synopsys, Inc. Mountain View, Calif.).